1. Field of the Invention
The present invention relates generally to flip-chip packaging processes, and more particularly, to a flip-chip packaging process utilizing an improved probe tip design for implementing a probing process.
2. Description of the Prior Art
For chip-to-carrier interconnection, IBM uses its Controlled Collapse Chip Connection (C4) technology, widely known as Flip-Chip Attach (FCA). C4 and flip-chip provide high I/O density, uniform chip power distribution, superior cooling capability, and high reliability. Originally developed for use with ceramic carriers in connection with the Solid Logic Technology (SLT) introduced by IBM in the early 1960s, C4 is a process that uses 97/3% PbSn solder balls with diameters ranging from 100 to 125 microns as a chip-to-carrier interconnect. An array of these balls or bumps are arranged around the surface of a chip, either in an area or peripheral configuration. The chip is placed face down on a carrier that has been prepared with corresponding metallized pads that have been flashed with gold to prevent corrosion. When heat is applied, the solder re-flows to the pads.
Please refer to FIG. 1. FIG. 1 illustrates a conventional flip-chip packaging process flow. As shown in FIG. 1, typically, after finishing the fabrication of semiconductor devices on semiconductor wafers (Step 1), the semiconductor wafers are thereafter transferred to a subcontractor for bumping (Step 2). This bumping process usually takes 5 to 7 days, followed by a 2-day electrical probing test (Step 3) that is carried out in a testing house. After undergoing the electrical test, the wafers are then transferred to a package house in which microchips are placed face down on a substrate such as a printed circuit board that has been prepared with corresponding pads. When heat is applied, the solder re-flows to the pads and the chips are connected to substrates (Step 4). This flip-chip packaging process takes another 5 to 7 days.
However, the above-mentioned flip-chip packaging process flow encounters many problems. One of the problems in using the conventional flip-chip packaging process flow is that since the probing test is carried out after the bumping process (it needs 5 to 7 days to be finished as mentioned), the important yield feedback information is delayed for 5 to 7 days. When fabrication processes of this batch of wafers went wrong, this yield feedback information will only be known after the bumping process is done. Consequently, the risk is high for an IC chip manufacturer. A second problem in utilizing the conventional flip-chip packaging process flow is that the yield result covers both the fabrication processes of this batch of wafers and also the subsequent bumping process. Sometimes, it is difficult to distinguish the source of the yield loss. Further, according to the prior art flip-chip packaging process flow, it takes 12 to 16 days in total to finish flip-chip packaging. As mentioned, the wafers have to be transferred from wafer foundry to a subcontractor for bumping, then to a testing house for probing test, then to package house for chip-substrate connection. Accordingly, there is a need to provide a new, reliable and simplified flip-chip packaging process flow for the chipmakers to solve the above-mentioned problems.